Release 12.1 - xst M.53d (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> 
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.30 secs
 
--> 
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.31 secs
 
--> 
Reading design: MSX_SRAM_mapper_512K.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "MSX_SRAM_mapper_512K.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "MSX_SRAM_mapper_512K"
Output Format                      : NGC
Target Device                      : XC9500 CPLDs

---- Source Options
Top Module Name                    : MSX_SRAM_mapper_512K
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Area
Optimization Effort                : 1
Library Search Order               : MSX_SRAM_mapper_512K.lso
Keep Hierarchy                     : YES
Netlist Hierarchy                  : as_optimized
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Verilog 2001                       : YES

---- Other Options
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/alwin/Xilinx/MSX_SRAM_mapper_512K/MSX_SRAM_mapper_512K.vhf" in Library work.
Entity <AND6_MXILINX_MSX_SRAM_mapper_512K> compiled.
Entity <AND6_MXILINX_MSX_SRAM_mapper_512K> (Architecture <BEHAVIORAL>) compiled.
Entity <M2_1E_MXILINX_MSX_SRAM_mapper_512K> compiled.
Entity <M2_1E_MXILINX_MSX_SRAM_mapper_512K> (Architecture <BEHAVIORAL>) compiled.
Entity <M2_1_MXILINX_MSX_SRAM_mapper_512K> compiled.
Entity <M2_1_MXILINX_MSX_SRAM_mapper_512K> (Architecture <BEHAVIORAL>) compiled.
Entity <M4_1E_MXILINX_MSX_SRAM_mapper_512K> compiled.
Entity <M4_1E_MXILINX_MSX_SRAM_mapper_512K> (Architecture <BEHAVIORAL>) compiled.
Entity <MSX_SRAM_mapper_512K> compiled.
Entity <MSX_SRAM_mapper_512K> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <MSX_SRAM_mapper_512K> in library <work> (architecture <BEHAVIORAL>).

Analyzing hierarchy for entity <AND6_MXILINX_MSX_SRAM_mapper_512K> in library <work> (architecture <BEHAVIORAL>).

Analyzing hierarchy for entity <M4_1E_MXILINX_MSX_SRAM_mapper_512K> in library <work> (architecture <BEHAVIORAL>).

Analyzing hierarchy for entity <M2_1E_MXILINX_MSX_SRAM_mapper_512K> in library <work> (architecture <BEHAVIORAL>).

Analyzing hierarchy for entity <M2_1_MXILINX_MSX_SRAM_mapper_512K> in library <work> (architecture <BEHAVIORAL>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <MSX_SRAM_mapper_512K> in library <work> (Architecture <BEHAVIORAL>).
    Set user-defined property "HU_SET =  and_a2to7_13" for instance <and_a2to7> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  d0_selector_3" for instance <d0_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  d1_selector_5" for instance <d1_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  d2_selector_7" for instance <d2_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  d3_selector_9" for instance <d3_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  d4_selector_11" for instance <d4_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  ma14_selector_4" for instance <ma14_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  ma15_selector_6" for instance <ma15_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  ma16_selector_8" for instance <ma16_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  ma17_selector_10" for instance <ma17_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  ma18_selector_12" for instance <ma18_selector> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  1" for instance <store_fc_bit0> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  1" for instance <store_fc_bit1> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fc_bit2> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fc_bit3> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fc_bit4> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fd_bit0> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  1" for instance <store_fd_bit1> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fd_bit2> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fd_bit3> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fd_bit4> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  1" for instance <store_fe_bit0> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fe_bit1> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fe_bit2> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fe_bit3> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_fe_bit4> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_ff_bit0> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_ff_bit1> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_ff_bit2> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_ff_bit3> in unit <MSX_SRAM_mapper_512K>.
    Set user-defined property "INIT =  0" for instance <store_ff_bit4> in unit <MSX_SRAM_mapper_512K>.
Entity <MSX_SRAM_mapper_512K> analyzed. Unit <MSX_SRAM_mapper_512K> generated.

Analyzing Entity <AND6_MXILINX_MSX_SRAM_mapper_512K> in library <work> (Architecture <BEHAVIORAL>).
Entity <AND6_MXILINX_MSX_SRAM_mapper_512K> analyzed. Unit <AND6_MXILINX_MSX_SRAM_mapper_512K> generated.

Analyzing Entity <M4_1E_MXILINX_MSX_SRAM_mapper_512K> in library <work> (Architecture <BEHAVIORAL>).
    Set user-defined property "HU_SET =  U1_2" for instance <U1> in unit <M4_1E_MXILINX_MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  U2_1" for instance <U2> in unit <M4_1E_MXILINX_MSX_SRAM_mapper_512K>.
    Set user-defined property "HU_SET =  U3_0" for instance <U3> in unit <M4_1E_MXILINX_MSX_SRAM_mapper_512K>.
Entity <M4_1E_MXILINX_MSX_SRAM_mapper_512K> analyzed. Unit <M4_1E_MXILINX_MSX_SRAM_mapper_512K> generated.

Analyzing Entity <M2_1E_MXILINX_MSX_SRAM_mapper_512K> in library <work> (Architecture <BEHAVIORAL>).
Entity <M2_1E_MXILINX_MSX_SRAM_mapper_512K> analyzed. Unit <M2_1E_MXILINX_MSX_SRAM_mapper_512K> generated.

Analyzing Entity <M2_1_MXILINX_MSX_SRAM_mapper_512K> in library <work> (Architecture <BEHAVIORAL>).
Entity <M2_1_MXILINX_MSX_SRAM_mapper_512K> analyzed. Unit <M2_1_MXILINX_MSX_SRAM_mapper_512K> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <AND6_MXILINX_MSX_SRAM_mapper_512K>.
    Related source file is "/home/alwin/Xilinx/MSX_SRAM_mapper_512K/MSX_SRAM_mapper_512K.vhf".
Unit <AND6_MXILINX_MSX_SRAM_mapper_512K> synthesized.


Synthesizing Unit <M2_1E_MXILINX_MSX_SRAM_mapper_512K>.
    Related source file is "/home/alwin/Xilinx/MSX_SRAM_mapper_512K/MSX_SRAM_mapper_512K.vhf".
Unit <M2_1E_MXILINX_MSX_SRAM_mapper_512K> synthesized.


Synthesizing Unit <M2_1_MXILINX_MSX_SRAM_mapper_512K>.
    Related source file is "/home/alwin/Xilinx/MSX_SRAM_mapper_512K/MSX_SRAM_mapper_512K.vhf".
Unit <M2_1_MXILINX_MSX_SRAM_mapper_512K> synthesized.


Synthesizing Unit <M4_1E_MXILINX_MSX_SRAM_mapper_512K>.
    Related source file is "/home/alwin/Xilinx/MSX_SRAM_mapper_512K/MSX_SRAM_mapper_512K.vhf".
Unit <M4_1E_MXILINX_MSX_SRAM_mapper_512K> synthesized.


Synthesizing Unit <MSX_SRAM_mapper_512K>.
    Related source file is "/home/alwin/Xilinx/MSX_SRAM_mapper_512K/MSX_SRAM_mapper_512K.vhf".
Unit <MSX_SRAM_mapper_512K> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 20
 Flip-Flops                                            : 20

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <MSX_SRAM_mapper_512K> ...
  implementation constraint: INIT=1	 : store_fc_bit0
  implementation constraint: INIT=1	 : store_fc_bit1
  implementation constraint: INIT=0	 : store_fc_bit2
  implementation constraint: INIT=0	 : store_fc_bit3
  implementation constraint: INIT=0	 : store_fc_bit4
  implementation constraint: INIT=0	 : store_fd_bit0
  implementation constraint: INIT=1	 : store_fd_bit1
  implementation constraint: INIT=0	 : store_fd_bit2
  implementation constraint: INIT=0	 : store_fd_bit3
  implementation constraint: INIT=0	 : store_fd_bit4
  implementation constraint: INIT=1	 : store_fe_bit0
  implementation constraint: INIT=0	 : store_fe_bit1
  implementation constraint: INIT=0	 : store_fe_bit2
  implementation constraint: INIT=0	 : store_fe_bit3
  implementation constraint: INIT=0	 : store_fe_bit4
  implementation constraint: INIT=0	 : store_ff_bit0
  implementation constraint: INIT=0	 : store_ff_bit1
  implementation constraint: INIT=0	 : store_ff_bit2
  implementation constraint: INIT=0	 : store_ff_bit3
  implementation constraint: INIT=0	 : store_ff_bit4

Optimizing unit <AND6_MXILINX_MSX_SRAM_mapper_512K> ...

Optimizing unit <M2_1E_MXILINX_MSX_SRAM_mapper_512K> ...

Optimizing unit <M2_1_MXILINX_MSX_SRAM_mapper_512K> ...

Optimizing unit <M4_1E_MXILINX_MSX_SRAM_mapper_512K> ...
WARNING:Xst:2036 - Inserting OBUF on port <Busdir> driven by black box <NAND3B2>. Possible simulation mismatch.

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : MSX_SRAM_mapper_512K.ngr
Top Level Output File Name         : MSX_SRAM_mapper_512K
Output Format                      : NGC
Optimization Goal                  : Area
Keep Hierarchy                     : YES
Target Technology                  : XC9500 CPLDs
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 24

Cell Usage :
# BELS                             : 69
#      AND2                        : 10
#      AND3                        : 21
#      AND4                        : 1
#      GND                         : 1
#      INV                         : 5
#      OR2                         : 30
#      VCC                         : 1
# FlipFlops/Latches                : 20
#      FDCE                        : 20
# IO Buffers                       : 24
#      IBUF                        : 13
#      IOBUFE                      : 5
#      OBUF                        : 6
# Others                           : 35
#      AND2B1                      : 10
#      AND3B1                      : 20
#      NAND3B2                     : 1
#      NAND4B2                     : 1
#      NAND4B3                     : 2
#      NAND4B4                     : 1
=========================================================================


Total REAL time to Xst completion: 55.00 secs
Total CPU time to Xst completion: 36.91 secs
 
--> 


Total memory usage is 150084 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

